Test Point Insertion to Improve
BIST Performance, and to Reduce
ATPG Test Time & Data Volume
By Joroen Geuzebroek
Delft University Press
215 pages, Illustrated, 6 1/2" x 9 1/2"
$67.50 Paper Original
OUT OF PRINT
The main subject of this dissertation is to facilitate structural testing by means of Test Point Insertion (TPI) for both on-chip and off-chip tests. Efficient production testing is frequently hampered because current complex digital designs require too large test sets, even with powerful ATPG tools that generate compact test sets. An alternative is Built-In Self-Test (BIST); by embedding the test on-chip, expensive test equipment costs and test time can be reduced. However, BIST approaches often suffer from fault coverage problems, due to random pattern resistant faults. These problems can successfully be reduced, or even eliminated, by means of Test Point Insertion (TPI).
In this dissertation we analyze three state-of-the-art TPI methods on their fault coverage improvement for BIST and develop a novel TPI algorithm that results in even better fault coverage improvement. This novel TPI algorithm has not only been developed to be applicable to Boolean circuits, but also to three-state designs. Results of several ISCAS and Philips industrial benchmark circuits show that the proposed TPI algorithm is applicable to both small Boolean circuits as well as to large complex industrial designs. TPI for BIST not only improves PR fault coverage; it will be shown that TPI also results in more compact ATPG test set sizes. In this dissertation new TPI methods are presented that are aimed at solving ATPG specific testability problems, such that the ATPG test set sizes and CPU times can be reduced much further. These TPI methods are not only applicable to SAF ATPG; it has been demonstrated that also for gate-delay fault ATPG significant ATPG test set size reduction, ATPG fault coverage improvement and ATPG CPU time reduction can be achieved. The new TPI methods have been implemented as part of the Delft Advanced Test Generation System and AMSAL, and are currently being used within Philips as part of their logic test tool set.
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